The present invention relates, in general, to semiconductor memory devices and, more particularly, to a write apparatus of Double Data Rate Synchronous DRAM (DDR SDRAM).
Recently, DDR SDRAM has been in the spotlight since it has a high operating speed compared with conventional SDRAM. In general, in DDR SDRAM, data are input and output in synchronization with the rising or falling edge of a clock. However, four register signals must be latched in parallel. It increases the number of signals, resulting in an increased area of the circuit. Furthermore, since the number of operating circuits is increased, a necessary amount of current is increased.
FIG. 1 is a block diagram schematically showing a data write apparatus in conventional DDR SDRAM. The data write apparatus includes a data strobe buffer 110, a first delay unit 120, a data input buffer 130, a second delay unit 140, latch units 151 to 153 and 161 to 164, and a global I/O transfer unit 170. The data strobe buffer 110 buffers a data strobe pulse DQS in response to an enable signal endin. The first delay unit 120 outputs a rising sense signal DSRP and a falling sense signal DSFP in response to a strobe output pulse DSP output from the data strobe buffer 110. The data input buffer 130 has an input terminal DQ for receiving and buffering input data in response to the enable signal endin. The second delay unit 140 controls set-up or hold characteristics and allocates data to a first input line DIN1 in response to an input strobe pulse DQP. The first latch 151 latches data and transfers the data to a second input line DIN2, in response to the rising sense signal DSRP. The second latch 152 latches data and allocates the data to a second data line DL2 in response to the falling sense signal DSFP. The third latch 153 latches data and allocates the data to a first data line DL1 in response to the falling sense signal DSFP. The fourth latch 161 latches data in response to the rising sense signal DSRP. The fifth latch 162 latches data in response to the rising sense signal DSRP. The sixth latch 163 latches data and allocates the data to the third data line DL3 in response to the falling sense signal DSFP. The seventh latch 164 latches data and allocates the data to the fourth data line DL4 in response to the falling sense signal DSFP. The global I/O transfer unit 170 outputs the data allocated to the first to fourth data lines DL1 to DL4 to a global I/O bus GIO in response to a strobe pulse DCLK. FIG. 2 is a timing diagram illustrating a data write operation of the data write apparatus show in FIG. 1. The rising sense signal DSRP is generated in synchronization with the rising edge of the data strobe pulse DQS. The falling sense signal DSFP is generated in synchronization with the falling edge of the data strobe pulse DQS. The data D1 to D4 are input to the data input buffer 130 through the input terminal DQ. The input data are latched in the first latch 151 by the rising sense signal DSRP through the second delay unit 140. The data are then latched in the third latch 153 by the falling sense signal DSFP and are then allocated to the first data line DL1. At this time, the second data D2 are latched in the second latch 152 in synchronization with the falling sense signal DSFP and are allocated to the second data line DL2. In a next rising clock, the first and second data D1 and D2 allocated to the first and second data lines DL1 and DL2 are respectively latched in the fourth latch 161 and the fifth latch 162. At the same time, the third data D3 are latched in the first latch 151. The third data D3 are latched in the third latch 153 and are allocated to the first data line DL1 by a next falling sense signal DSFP. The fourth data D4 are latched in the second latch 152 and are allocated to the second data line DL2 by the next falling sense signal DSFP. Furthermore, the first and second data D1 and D2 are latched in the sixth and seventh latches 163 and 164, respectively, and are allocated to the third data line DL3 and the fourth data line DL4, respectively. Accordingly, the first to fourth data lines DL1 to DL4 are respectively allocated with the third data D3, the fourth data D4, the first data DL1 and the second data DL2. Furthermore, if the strobe pulse DCLK is enabled, the data D1 to D4 are all output to the global I/O line GIO. Through the above operation, the data are latched through the third data line DL3, the fourth data line DL4, the first data line DL1, and the second data line DL2 in parallel. Accordingly, this method is called a parallel register scheme. However, this scheme increases the area of a circuit since the number of lines for transferring signals is increased. Furthermore, since the number of operating circuits increases, power consumption is increased.